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		<id>http://simhard.com/wiki/index.php?action=history&amp;feed=atom&amp;title=VHDL-2019</id>
		<title>VHDL-2019 - История изменений</title>
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		<updated>2026-06-08T19:43:01Z</updated>
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		<id>http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7552&amp;oldid=prev</id>
		<title>ANA в 18:54, 27 апреля 2021</title>
		<link rel="alternate" type="text/html" href="http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7552&amp;oldid=prev"/>
				<updated>2021-04-27T18:54:11Z</updated>
		
		<summary type="html">&lt;p&gt;&lt;/p&gt;
&lt;table class='diff diff-contentalign-left'&gt;
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			&lt;td colspan='2' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;← Предыдущая&lt;/td&gt;
			&lt;td colspan='2' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;Версия 18:54, 27 апреля 2021&lt;/td&gt;
			&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 8:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 8:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://osvvm.org/archives/1806 VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment]&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://osvvm.org/archives/1806 VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment]&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019&amp;#160; от создателей текстового редактора Sigasi&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019&amp;#160; от создателей текстового редактора Sigasi&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;−&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;del style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;* [https://electronics.stackexchange.com/questions/4482/vhdl-converting-from-an-integer-type-to-a-std-logic-vector VHDL-2019 example of conversion from integer to std_logic_vector] -&amp;gt; [https://www.edaplayground.com/x/qJLb edaplayground Example: VHDL-2019 handle of receiver of return value]&lt;/del&gt;&lt;/div&gt;&lt;/td&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* https://opensource.ieee.org/vasg/Packages - исходные коды IEEE-пакетов VHDL&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* https://opensource.ieee.org/vasg/Packages - исходные коды IEEE-пакетов VHDL&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;=== EDA Playground examples ===&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;* [https://www.edaplayground.com/x/REB3 My exaple of mode view usage]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;* [https://electronics.stackexchange.com/questions/4482/vhdl-converting-from-an-integer-type-to-a-std-logic-vector VHDL-2019 example of conversion from integer to std_logic_vector] -&amp;gt; [https://www.edaplayground.com/x/qJLb edaplayground Example: VHDL-2019 handle of receiver of return value]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;* [https://www.edaplayground.com/x/4JZQ VHDL-2019 private and alas in protected types]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;* [https://www.edaplayground.com/x/2gEF VHDL-2019 std.env]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;=== Основные нововведения в VHDL-2019 ===&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;=== Основные нововведения в VHDL-2019 ===&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 28:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 33:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;[[Категория:VHDL]]&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;[[Категория:VHDL]]&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;[[Категория:VHDL-2019]]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>ANA</name></author>	</entry>

	<entry>
		<id>http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7551&amp;oldid=prev</id>
		<title>ANA в 18:44, 27 апреля 2021</title>
		<link rel="alternate" type="text/html" href="http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7551&amp;oldid=prev"/>
				<updated>2021-04-27T18:44:05Z</updated>
		
		<summary type="html">&lt;p&gt;&lt;/p&gt;
&lt;table class='diff diff-contentalign-left'&gt;
				&lt;col class='diff-marker' /&gt;
				&lt;col class='diff-content' /&gt;
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			&lt;td colspan='2' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;← Предыдущая&lt;/td&gt;
			&lt;td colspan='2' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;Версия 18:44, 27 апреля 2021&lt;/td&gt;
			&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 8:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 8:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://osvvm.org/archives/1806 VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment]&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://osvvm.org/archives/1806 VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment]&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019&amp;#160; от создателей текстового редактора Sigasi&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019&amp;#160; от создателей текстового редактора Sigasi&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;−&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&amp;#160;&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;* [https://electronics.stackexchange.com/questions/4482/vhdl-converting-from-an-integer-type-to-a-std-logic-vector VHDL-2019 example of conversion from integer to std_logic_vector] -&amp;gt; [https://www.edaplayground.com/x/qJLb edaplayground Example: VHDL-2019 handle of receiver of return value]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* https://opensource.ieee.org/vasg/Packages - исходные коды IEEE-пакетов VHDL&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* https://opensource.ieee.org/vasg/Packages - исходные коды IEEE-пакетов VHDL&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>ANA</name></author>	</entry>

	<entry>
		<id>http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7550&amp;oldid=prev</id>
		<title>ANA в 17:32, 27 апреля 2021</title>
		<link rel="alternate" type="text/html" href="http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7550&amp;oldid=prev"/>
				<updated>2021-04-27T17:32:26Z</updated>
		
		<summary type="html">&lt;p&gt;&lt;/p&gt;
&lt;table class='diff diff-contentalign-left'&gt;
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			&lt;td colspan='2' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;← Предыдущая&lt;/td&gt;
			&lt;td colspan='2' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;Версия 17:32, 27 апреля 2021&lt;/td&gt;
			&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 6:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Строка 6:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* https://standards.ieee.org/standard/1076-2019.html Ссылка на стандарт языка VHDL-2019&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* https://standards.ieee.org/standard/1076-2019.html Ссылка на стандарт языка VHDL-2019&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://osvvm.org/archives/1657 VHDL-2019: the Users Standard] - Краткое описание нововведений VHDL-2019 на сайте osvvm.org&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://osvvm.org/archives/1657 VHDL-2019: the Users Standard] - Краткое описание нововведений VHDL-2019 на сайте osvvm.org&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&amp;#160;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;* [https://osvvm.org/archives/1806 VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019&amp;#160; от создателей текстового редактора Sigasi&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019&amp;#160; от создателей текстового редактора Sigasi&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;&amp;#160;&lt;/td&gt;&lt;td style=&quot;background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>ANA</name></author>	</entry>

	<entry>
		<id>http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7514&amp;oldid=prev</id>
		<title>ANA: Новая страница: « === Полезные ссылки:=== * [https://www.plc2.com/training/detail/new-features-in-vhdl-2019-webinar Webinar]: New Features in VHDL 2019 - WEBINAR (т…»</title>
		<link rel="alternate" type="text/html" href="http://simhard.com/wiki/index.php?title=VHDL-2019&amp;diff=7514&amp;oldid=prev"/>
				<updated>2021-01-17T17:18:16Z</updated>
		
		<summary type="html">&lt;p&gt;Новая страница: « === Полезные ссылки:=== * [https://www.plc2.com/training/detail/new-features-in-vhdl-2019-webinar Webinar]: New Features in VHDL 2019 - WEBINAR (т…»&lt;/p&gt;
&lt;p&gt;&lt;b&gt;Новая страница&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&lt;br /&gt;
=== Полезные ссылки:===&lt;br /&gt;
* [https://www.plc2.com/training/detail/new-features-in-vhdl-2019-webinar Webinar]: New Features in VHDL 2019 - WEBINAR (требуется [https://attendee.gotowebinar.com/register/3850217452982579472 регистрация] для просмотра)&lt;br /&gt;
* http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/VHDL2017 - Описание изменений языка VHDL-2019&lt;br /&gt;
* https://vhdlwhiz.com/vhdl-2019/ - описание нововведений в VHDL-2019&lt;br /&gt;
* https://standards.ieee.org/standard/1076-2019.html Ссылка на стандарт языка VHDL-2019&lt;br /&gt;
* [https://osvvm.org/archives/1657 VHDL-2019: the Users Standard] - Краткое описание нововведений VHDL-2019 на сайте osvvm.org&lt;br /&gt;
* [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019  от создателей текстового редактора Sigasi&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
* https://opensource.ieee.org/vasg/Packages - исходные коды IEEE-пакетов VHDL&lt;br /&gt;
&lt;br /&gt;
=== Основные нововведения в VHDL-2019 ===&lt;br /&gt;
&lt;br /&gt;
* Interfaces (Mode views)&lt;br /&gt;
* Garbage collection&lt;br /&gt;
* 64-bit integers&lt;br /&gt;
* Conditional analysis&lt;br /&gt;
* Shared variables on entities&lt;br /&gt;
* Generics on protected types&lt;br /&gt;
* Generics on subprograms&lt;br /&gt;
* Partially connected vectors in port maps&lt;br /&gt;
* APIs&lt;br /&gt;
* New Attributes&lt;br /&gt;
* Anonymous Types&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
[[Категория:VHDL]]&lt;/div&gt;</summary>
		<author><name>ANA</name></author>	</entry>

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