Co-Simulation/Литература — различия между версиями

Текущая версия на 13:25, 22 декабря 2013

Co-Simulation

Литература

Литература

* PSL * VHDL * OS-VVM *

Содержание

1 Ссылки
- 1.1 for MES2014
2 Accelerating OVM/UVM Testbench Environments in Veloce [1]
3 NEW

Ссылки

http://www.bluespec.com/products/index.htm Bluespec Core Technology
- http://csg.csail.mit.edu/6.S078/6_S078_2012_www/resources/bsv_by_example.pdf BSV by Example book
- https://sites.google.com/a/bluespec.com/learning-bluespec/Home/BSV-Documentation BSV-Documentation
- http://www.bluespec.com/emulationinfrastructure/emulationinfrastructure.html Emulation Infrastructure

http://www.marcopolofpga.co.kr/html/01main_sub01.php?idx=12&PHPSESSID=b096164b3f02ddb0890df0559116f091 MECS ( MarcoPolo co- Emulation System )

http://www.xess.com/appnotes/xst3_video.php

SCE-MI (Standard Co-Emulation Modeling Interface)
- http://www.accellera.org/downloads/standards/sce-mi Download SCE-MI (Standard Co-Emulation Modeling Interface)
- Standard Co-Emulation Modeling Interface, Release 2.1 (2011-01-21)
- sce-mi-20-standard (вебинар verificationacademy)

Готовые решения:
- Aldec's HES™ Hardware Emulation Solutions
- alatek
  - Alatek Inc. Announces New LINUX Hardware Accelerator Speeds HDL Simulators
  - Alatek Boosts Performance of Mentor Graphics® HDL Simulators By 100x
Hardware Embedded Simulation (HES) includes the first year of software maintenance in the purchase price. HES products supporting 2 million FPGA gates start at $125,000. Various hardware configurations are available, and boards that support up to 6 million FPGA gates will be available in 4thQTR of 2001.
http://www.eve-team.com/ - Сейчас часть Synopsys
OpenIDEA
- ASIC Development Test Platform with Virtex-7 FPGA By Inrevium™
Новости
- Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform

Другое
- Моделирование HDL-проектов на мультипроцессорной системе

for MES2014

А.Пеженков, Д.Радченко. Аппаратные эмуляторы на платформе ZEBU компании EVE - Выпуск #4/2005 (pdf)

Accelerating OVM/UVM Testbench Environments in Veloce [1]

The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.

NEW

@@ Строка 1: / Строка 1: @@
 {{Co-Simulation TOC}}
-== [http://www.ftdichip.com/Products/ICs/FT2232H.htm FT2232H - Hi-Speed Dual USB UART/FIFO IC] ==
+* [http://www.ftdichip.com/Products/ICs/FT2232H.htm FT2232H - Hi-Speed Dual USB UART/FIFO IC]
-The FT2232H is FTDI’s 5th generation of USB devices.  The FT2232H is a USB 2.0 Hi-Speed (480Mb/s) to UART/FIFO IC.  It has the capability of being configured in a variety of industry standard serial or parallel interfaces.
+* [http://microsin.net/adminstuff/hardware/ft2232h-dual-uart-fifo-usb-converter.html полностью переведенный даташит FT2232H - Hi-Speed Dual USB UART/FIFO IC]
+* [http://kit-e.ru/articles/interface/2010_08_90.php http://kit-e.ru/articles/interface/2010_08_90.php]
-Building on the innovative features of the FT2232, the FT2232H has two multi-protocol synchronous serial engines (MPSSEs) which allow for communication using JTAG, I2C and SPI on two channels simultaneously.
+==Ссылки==
+* http://www.bluespec.com/products/index.htm Bluespec Core Technology
+** http://csg.csail.mit.edu/6.S078/6_S078_2012_www/resources/bsv_by_example.pdf BSV by Example book
+** https://sites.google.com/a/bluespec.com/learning-bluespec/Home/BSV-Documentation BSV-Documentation
+** http://www.bluespec.com/emulationinfrastructure/emulationinfrastructure.html Emulation Infrastructure
-The FT2232H is available in Pb-free (RoHS compliant) 64-pin LQFP and QFN packages.
+* http://www.marcopolofpga.co.kr/html/01main_sub01.php?idx=12&PHPSESSID=b096164b3f02ddb0890df0559116f091  MECS ( MarcoPolo co- Emulation System )
+* http://www.xess.com/appnotes/xst3_video.php
-=== Product Information ===
-* [http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf FT2232H Datasheet]
+* '''SCE-MI (Standard Co-Emulation Modeling Interface)'''
-* [http://www.ftdichip.com/Drivers/VCP.htm VCP Drivers]
+** http://www.accellera.org/downloads/standards/sce-mi Download SCE-MI (Standard Co-Emulation Modeling Interface)
-* [http://www.ftdichip.com/Drivers/D2XX.htm D2XX Drivers]
+** [http://www.accellera.org/downloads/standards/sce-mi/SCE_MI_v21-110112-final.pdf Standard Co-Emulation Modeling Interface, Release 2.1] (2011-01-21)
-* [http://www.ftdichip.com/Support/SoftwareExamples/MPSSE.htm  MPSSE Code Examples]
+** [https://verificationacademy.com/sessions/sce-mi-20-standard sce-mi-20-standard] (вебинар verificationacademy)
-* [http://www.ftdichip.com/Support/SoftwareExamples/MPSSE/LibMPSSE-I2C.htm LibMPSSE-I2C DLL]
-* [http://www.ftdichip.com/Support/SoftwareExamples/MPSSE/FTCJTAG.htm MPSSE JTAG DLL]
-* [http://www.ftdichip.com/Support/SoftwareExamples/MPSSE/FTCSPI.htm MPSSE SPI DLL]
+* '''Готовые решения:'''
+** [http://www.aldec.com/products/HES Aldec's HES™ Hardware Emulation Solutions]
+** alatek
+*** [http://www.design-reuse.com/news/2989/alatek-linux-hardware-accelerator-speeds-hdl-simulators.html Alatek Inc. Announces New LINUX Hardware Accelerator Speeds HDL Simulators]
+*** [http://www.design-reuse.com/news/695/alatek-boosts-performance-mentor-graphics-reg-hdl-simulators-100x.html Alatek Boosts Performance of Mentor Graphics® HDL Simulators By 100x]
+*::: Hardware Embedded Simulation (HES) includes the first year of software maintenance in the purchase price. HES products supporting 2 million FPGA gates start at $125,000. Various hardware configurations are available, and boards that support up to 6 million FPGA gates will be available in 4thQTR of 2001.
+*** [http://hardclub.donntu.edu.ua/rus/etc/hes.htm Hardware Embedded Simulation™ ({{Кр|На русском}})]
+** [http://www.cadence.com/products/sd/rapid_prototyping/pages/resources.aspx Rapid Prototyping Platform] (cadence)
+**[http://www.cadence.com/products/sd/palladium_series/pages/default.aspx '''Cadence Palladium XP''']
+**[http://www.eve-team.com/products/index.php '''EVE Zebu''']
+**[http://www.mentor.com/products/fv/emulation-systems/ '''Mentor Veloce''']
+**[http://www.synopsys.com/Tools/Verification/HardwareAssistedVerification/Pages/default.aspx '''Synopsys Confirma''']
+* http://www.eve-team.com/ - Сейчас часть Synopsys
+* [http://www.dynalith.com/doku.php?id=openidea OpenIDEA]
+** [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,719,1125&Prod=INREVIUM-7V-2000T  ASIC Development Test Platform with Virtex-7 FPGA By Inrevium™]
+* '''Новости'''
+** [http://www.aldec.com/en/company/news/2012-12-10/140 Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform]
-=== Key Hardware Features ===
+* Другое
+** [http://masters.donntu.edu.ua/2003/fvti/gez/diss/index.htm Моделирование HDL-проектов на мультипроцессорной системе]
-* Single chip USB to dual serial / parallel ports with a variety of configurations.
-*    Entire USB protocol handled on the chip. No USB specific firmware programming required.
-*    USB 2.0 High Speed (480Mbits/second) and Full Speed (12Mbits/second) compatible.
-*    Dual Multi-Protocol Synchronous Serial Engine (MPSSE) to simplify synchronous serial protocol (USB to JTAG, I2C, SPI or bit-bang) design.
-*    Dual independent UART or FIFO ports configurable using MPSSEs.
-*    Independent Baud rate generators.
-*    RS232/RS422/RS485 UART Transfer Data Rate up to 12Mbaud. (RS232 Data Rate limited by external level shifter).
-*    USB to parallel FIFO transfer data rate up to 10Mbyte/sec.
-*    Single channel synchronous FIFO mode for transfers up to 40 Mbytes/sec.
-*    CPU-style FIFO interface mode simplifies CPU interface design.
-*    MCU host bus emulation mode configuration option.
-*    Fast Opto-Isolated serial interface option.
-*    FTDI’s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases.
-*    Adjustable receive buffer timeout.
-*    Option for transmit and receive LED drive signals on each channel.
-*    Enhanced bit-bang Mode interface option with RD# and WR# strobes.
-*    FT245B-style FIFO interface option with bidirectional data bus and simple 4 wire handshake interface.
-*    Highly integrated design includes +1.8V LDO regulator for VCORE, integrated POR function and on chip clock multiplier PLL (12MHz – 480MHz).
-*    Asynchronous serial UART interface option with full hardware handshaking and modem interface signals.
-*    Fully assisted hardware or X-On / X-Off software handshaking.
-*    UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity.
-*    Auto-transmit enable control for RS485 serial applications using TXDEN pin.
-*    Operational configuration mode and USB Description strings configurable in external EEPROM over the USB interface.
-*    Configurable I/O drive strength (4,8,12 or 16mA) and slew rate.
-*    Low operating and USB suspend current.
-*    Supports bus powered, self powered and high-power bus powered USB configurations.
-*    UHCI/OHCI/EHCI host controller compatible.
-*    USB Bulk data transfer mode (512 byte packets in Hi-Speed mode).
-*    +1.8V (chip core) and +3.3V I/O interfacing (+5V Tolerant).
-*    Extended -40°C to 85°C industrial operating temperature range.
-*    Compact 64-LD Lead Free LQFP or LQFN package.
-*    +3.3V single supply operating voltage range.
+==== for MES2014 ====
-=== Application Areas ===
+* [http://www.electronics.ru/journal/article/903 А.Пеженков, Д.Радченко. ''Аппаратные эмуляторы на платформе ZEBU компании EVE'' - Выпуск #4/2005] ([http://www.electronics.ru/files/article_pdf/0/article_903_81.pdf pdf])
-* Single chip USB to dual channel UART (RS232, RS422 or RS485).
-* Single chip USB to dual channel FIFO.
+== Accelerating OVM/UVM Testbench Environments in Veloce [http://www.mentor.com/products/fv/emulation-systems/] ==
-* Single chip USB to dual channel JTAG.
+[[Файл:Veloce-ovm.png|left]]
-* Single chip USB to dual channel SPI.
-* Single chip USB to dual channel I2C.
+The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.
-* Single chip USB to dual channel Bit-Bang.
-* Single chip USB to dual combination of any of above interfaces.
+<br clear=all />
-* Single chip USB to Fast Serial Optic Interface.
-* Single chip USB to CPU target interface (as memory), double and independent.
+== NEW ==
-* Single chip USB to Host Bus Emulation (as CPU).
-* USB Audio and Low Bandwidth Video data transfer
-* PDA to USB data transfer
-* USB Smart Card Readers
-* USB Instrumentation
-* USB Industrial Control
-* USB MP3 Player Interface
-* USB FLASH Card Reader / Writers
-* Set Top Box PC - USB interface
-* USB Digital Camera Interface
-* USB Bar Code Readers

Co-Simulation/Литература — различия между версиями

Текущая версия на 13:25, 22 декабря 2013

Содержание

Ссылки

for MES2014

Accelerating OVM/UVM Testbench Environments in Veloce [1]

NEW

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