Co-Simulation/Литература — различия между версиями
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**[http://www.mentor.com/products/fv/emulation-systems/ '''Mentor Veloce'''] | **[http://www.mentor.com/products/fv/emulation-systems/ '''Mentor Veloce'''] | ||
**[http://www.synopsys.com/Tools/Verification/HardwareAssistedVerification/Pages/default.aspx '''Synopsys Confirma'''] | **[http://www.synopsys.com/Tools/Verification/HardwareAssistedVerification/Pages/default.aspx '''Synopsys Confirma'''] | ||
| + | * http://www.eve-team.com/ - Сейчас часть Synopsys | ||
* [http://www.dynalith.com/doku.php?id=openidea OpenIDEA] | * [http://www.dynalith.com/doku.php?id=openidea OpenIDEA] | ||
** [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,719,1125&Prod=INREVIUM-7V-2000T ASIC Development Test Platform with Virtex-7 FPGA By Inrevium™] | ** [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,719,1125&Prod=INREVIUM-7V-2000T ASIC Development Test Platform with Virtex-7 FPGA By Inrevium™] | ||
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* Другое | * Другое | ||
** [http://masters.donntu.edu.ua/2003/fvti/gez/diss/index.htm Моделирование HDL-проектов на мультипроцессорной системе] | ** [http://masters.donntu.edu.ua/2003/fvti/gez/diss/index.htm Моделирование HDL-проектов на мультипроцессорной системе] | ||
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| + | ==== for MES2014 ==== | ||
| + | * [http://www.electronics.ru/journal/article/903 А.Пеженков, Д.Радченко. ''Аппаратные эмуляторы на платформе ZEBU компании EVE'' - Выпуск #4/2005] ([http://www.electronics.ru/files/article_pdf/0/article_903_81.pdf pdf]) | ||
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| + | == Accelerating OVM/UVM Testbench Environments in Veloce [http://www.mentor.com/products/fv/emulation-systems/] == | ||
| + | [[Файл:Veloce-ovm.png|left]] | ||
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| + | The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification. | ||
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| + | == NEW == | ||
Текущая версия на 13:25, 22 декабря 2013
- Техническое задание
- Описание FT2232H
- Описание FT232H
- (TUMPA) TIAO USB Multi Protocol Adapter
- (TUMPA) Litle
- Описание макета
- Примеры кода
Литература
- Литература
- FT2232H - Hi-Speed Dual USB UART/FIFO IC
- полностью переведенный даташит FT2232H - Hi-Speed Dual USB UART/FIFO IC
- http://kit-e.ru/articles/interface/2010_08_90.php
Содержание |
Ссылки
- http://www.bluespec.com/products/index.htm Bluespec Core Technology
- http://csg.csail.mit.edu/6.S078/6_S078_2012_www/resources/bsv_by_example.pdf BSV by Example book
- https://sites.google.com/a/bluespec.com/learning-bluespec/Home/BSV-Documentation BSV-Documentation
- http://www.bluespec.com/emulationinfrastructure/emulationinfrastructure.html Emulation Infrastructure
- http://www.marcopolofpga.co.kr/html/01main_sub01.php?idx=12&PHPSESSID=b096164b3f02ddb0890df0559116f091 MECS ( MarcoPolo co- Emulation System )
- SCE-MI (Standard Co-Emulation Modeling Interface)
- http://www.accellera.org/downloads/standards/sce-mi Download SCE-MI (Standard Co-Emulation Modeling Interface)
- Standard Co-Emulation Modeling Interface, Release 2.1 (2011-01-21)
- sce-mi-20-standard (вебинар verificationacademy)
- Готовые решения:
- Hardware Embedded Simulation (HES) includes the first year of software maintenance in the purchase price. HES products supporting 2 million FPGA gates start at $125,000. Various hardware configurations are available, and boards that support up to 6 million FPGA gates will be available in 4thQTR of 2001.
- http://www.eve-team.com/ - Сейчас часть Synopsys
- OpenIDEA
- Новости
for MES2014
Accelerating OVM/UVM Testbench Environments in Veloce [1]
The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.
