BIT-Cup 2015 (1 part) — вопросы

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
constant s : std_logic_vector( 3 downto 0 ) := "1001";
signal   c : std_logic_vector( 1 downto 0 );
begin
	c <= a & b;
	q <= s( conv_integer( c ) );
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	c : in  std_logic;
	d : in  std_logic_vector( 1 downto 0 );
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
begin
	process(a,b,c,d)
	begin
		if d="00" then
			q <= a;
		elsif d="01" then
			q <= b;
		elsif d="10" then
			q <= c;
		end if;
	end process;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	c : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
signal s : std_logic;
begin
	process(a,b,c)
	begin
		if rising_edge( a ) then
			if ( b = '1' ) then
				s <= c;
			end if;
		else
			s <= '0';
		end if;
	end process;
	q <= s;
end behavioral;

entity dev is
port(
	a : in  std_logic_vector( 3 downto 0 );
	q : out std_logic_vector( 1 downto 0 );
	g : out std_logic
);
end dev;
 
architecture behavioral of dev is
begin
	process( a )
	variable v: std_logic_vector( 1 downto 0 );
	begin
		v := "00";
		for i in 3 downto 0 loop
			if ( a(i)='1' ) then
				v := conv_std_logic_vector( i, 2 );
				g <= '1';
				exit;
			else
				g <= '0';
			end if;
		end loop;
		q <= v;
	end process;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
signal s : std_logic;
begin
	process( a,b )
	begin
		if ( a='1' ) then s <= '0'; end if;
		if ( a='0' ) then s <= b;   end if;
	end process;
	q <= s;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
begin
	process( a,b )
	begin
		if a='1' then
			if b='1' then
				q <= '1';
			else
				q <= '0';
			end if;
		else 
			q <= '0';
		end if;
	end process;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	c : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
signal s : std_logic_vector( 4 downto 0 );
begin
	sch: for i in 4 downto 1 generate
		s( i-1 ) <= ( s( i ) and c ) when ( rising_edge( a ) );
	end generate;
	s( 4 ) <= b;
	q <= s( 0 );
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a,b,c,d : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
signal s : std_logic;
begin
	process( a,b,c,d,s )
	begin
		if ( d = '1' ) then
			s <= '0';
		elsif falling_edge( a ) then
			if ( b = '1' ) then
				if ( c = '1' ) then
					s <= not s;
				else
					s <= '1';
				end if;
			elsif ( c = '1' ) then
				s <= '0';				
			end if;
		end if;
	end process;
	q <= s;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity dev is
generic ( g : std_logic_vector := "101010000" );
port(
	q : out integer
);
end dev;
 
architecture behavioral of dev is
begin
	q <= g'high;
 
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
 
entity dev is
port(
	a : in  std_logic;
	b : in  std_logic;
	q : out std_logic
);
end dev;
 
architecture behavioral of dev is
signal s : std_logic;
begin
	s <= a when b='0' else '1';
	q <= s when b='1' else 'Z';
end behavioral;