Co-Simulation/Литература

Ссылки сюда (13) →

Co-Simulation

• Техническое задание
• Описание FT2232H
• Описание FT232H
• (TUMPA) TIAO USB Multi Protocol Adapter
• (TUMPA) Litle
  • Компиляция и запуск в QuestaSim
• Описание макета
• Примеры кода

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Литература

• Литература

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• Словарь терминов
• Дневник
• История проекта
• Схема эмулятора
• Схема эмулятора на примере
• Схема эмулятора

* PSL * VHDL * OS-VVM *

• FT2232H - Hi-Speed Dual USB UART/FIFO IC
• полностью переведенный даташит FT2232H - Hi-Speed Dual USB UART/FIFO IC
• http://kit-e.ru/articles/interface/2010_08_90.php

Ссылки

• http://www.bluespec.com/products/index.htm Bluespec Core Technology
  • http://csg.csail.mit.edu/6.S078/6_S078_2012_www/resources/bsv_by_example.pdf BSV by Example book
  • https://sites.google.com/a/bluespec.com/learning-bluespec/Home/BSV-Documentation BSV-Documentation
  • http://www.bluespec.com/emulationinfrastructure/emulationinfrastructure.html Emulation Infrastructure

• http://www.marcopolofpga.co.kr/html/01main_sub01.php?idx=12&PHPSESSID=b096164b3f02ddb0890df0559116f091 MECS ( MarcoPolo co- Emulation System )

• http://www.xess.com/appnotes/xst3_video.php

• SCE-MI (Standard Co-Emulation Modeling Interface)
  • http://www.accellera.org/downloads/standards/sce-mi Download SCE-MI (Standard Co-Emulation Modeling Interface)
  • Standard Co-Emulation Modeling Interface, Release 2.1 (2011-01-21)
  • sce-mi-20-standard (вебинар verificationacademy)

• Готовые решения:
  • Aldec's HES™ Hardware Emulation Solutions
  • alatek
    • Alatek Inc. Announces New LINUX Hardware Accelerator Speeds HDL Simulators
    • Alatek Boosts Performance of Mentor Graphics® HDL Simulators By 100x

  Hardware Embedded Simulation (HES) includes the first year of software maintenance in the purchase price. HES products supporting 2 million FPGA gates start at $125,000. Various hardware configurations are available, and boards that support up to 6 million FPGA gates will be available in 4thQTR of 2001.

  • • Hardware Embedded Simulation™ (На русском)
  • Rapid Prototyping Platform (cadence)
  • Cadence Palladium XP
  • EVE Zebu
  • Mentor Veloce
  • Synopsys Confirma
• http://www.eve-team.com/ - Сейчас часть Synopsys
• OpenIDEA
  • ASIC Development Test Platform with Virtex-7 FPGA By Inrevium™
• Новости
  • Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform

• Другое
  • Моделирование HDL-проектов на мультипроцессорной системе

for MES2014

• А.Пеженков, Д.Радченко. Аппаратные эмуляторы на платформе ZEBU компании EVE - Выпуск #4/2005 (pdf)

Accelerating OVM/UVM Testbench Environments in Veloce [1]

The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.