ПТСиПЦУвСБ/Лекция 4 — различия между версиями

Версия 20:45, 16 марта 2014

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Типы данных языка VHDL

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Авдеев Н.А.

Нижний колонтитул

ПТСиПЦУвСБ/Лекция 4

Дополнительный нижний колонтитул

Авдеев Н.А., 18:45, 25 марта 2014

Слайд: Содержание

• Тип [un]signed пакета numeric_std
• Описание комбинационных схем на языке VHDL
• оператор generic и generate

Слайд: Формальный синтаксис декларации generic

entity_declaration ⇐
  entity identifier is
    [ generic ( generic_interface_list ) ; ]
    [ port ( port_interface_list ) ; ]
    { entity_declarative_item }
  [ begin
    { concurrent_assertion_statement
       | passive_concurrent_procedure_call_statement
       | passive_process_statement } ]
  end [ entity ] [ identifier ] ;

 interface_list ⇐ interface_declaration { ; ... }

 interface_declaration ⇐
    identifier { , ... } : subtype_indication [ := expression ]

Слайд: Пример 1 (generic)

entity and2 is
  generic ( Tpd : time );
  port ( a, b : in std_logic; y : out std_logic );
end entity and2;

architecture simple of and2 is
begin
  and2_function :
    y <= a and b after Tpd;
end architecture simple;

Оператор port map

instantiation_label : component_name port map (port list);

instantiation_label :
 [ component ] component_name
 | entity entity_name [ ( architecture_identifier ) ]
 | configuration configuration_name
  [ generic map ( generic_association_list ) ]
  [ port map (  [ port_name => ] signal_name [, [ port_name => ] signal_name]... ) ] ;

Пример:

gate1 : and2                                 -- [ component ] component_name
  generic map ( Tpd => 2 ns )
  port map ( a => sig1,
             b => sig2,
             y => sig_out );

gate2 : entity work.and2(simple)             -- entity entity_name [ ( architecture_identifier ) ]
  generic map ( Tpd => 3 ns )
  port map ( a => a1, b => b1, y => sig1 );

Слайд: Пример 2 (generic)

entity control_unit is
  generic ( Tpd_clk_out, Tpw_clk : delay_length;
            debug : boolean := false );
  port ( clk   : in std_logic;
         ready : in std_logic;
         control1, control2 : out std_logic );
end entity control_unit;
. . . 
generic map ( 200 ps, 1500 ps, false )
generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
generic map ( 200 ps, 1500 ps, debug => open )

Слайд: Пример 3 (generic)

entity reg is
  generic ( width : positive );
  port ( d : in std_logic_vector(width - 1 downto 0);
         q : out std_logic_vector(width - 1 downto 0);
         clk, reset : in std_logic );
end entity reg;

architecture behavioral of reg is
begin
  behavior : process (clk, reset) is
    constant zero : std_logic_vector(width - 1 downto 0) := (others => '0');
  begin
    if reset = '1' then
      q <= zero;
    elsif rising_edge(clk) then
      q <= d;
    end if;
  end process behavior;
end architecture behavioral;

Слайд: Расширение VHDL-2008 Generic Types

entity generic_mux2 is
  generic ( type data_type );
  port
    ( sel  : in bit;
      a, b : in data_type;
      z    : out data_type );
end entity generic_mux2;

architecture rtl of mux2 is
begin
  z <= a when not sel else b;
end architecture rtl;

. . .

signal sel_bit, a_bit, b_bit, z_bit : std_logic;
. . .
bit_mux : entity work.generic_mux2(rtl)
  generic map ( data_type => std_logic )
  port map
    ( sel => sel_bit, a => a_bit, b => b_bit,
      z => z_bit );

Слайд: Конструкция generate

for_generate_statement ⇐
  Метка_generate :
    for идентификатор in описание_диапазона generate
        [ { Декларативная_часть }
       begin ]
         { параллельные_операторы }
     [ end ; ]
    end generate [ Метка_generate ] ;

описание_диапазона ⇐
   discrete_subtype_indication
 | range_attribute_name
 | simple_expression ( to | downto ) simple_expression

Слайд: Пример (generate)

library ieee; use ieee.std_logic_1164.all;
entity register_tristate is
  generic ( width : positive );
  port ( clock      : in  std_logic;
         out_enable : in  std_logic;
         data_in    : in  std_logic_vector(width - 1 downto 0);
         data_out   : out std_logic_vector(width - 1 downto 0) );
end entity register_tristate;

architecture cell_level of register_tristate is
  component D_flipflop is
    port ( clk : in std_logic; 
           d   : in std_logic;
           q   : out std_logic );
  end component D_flipflop;
  component tristate_buffer is
    port ( a  : in std_logic;
           en : in std_logic;
           y  : out std_logic );
  end component tristate_buffer;
begin
  cell_array : for bit_index in width - 1 downto 0 generate
    signal data_unbuffered : std_logic;
  begin
    cell_storage : component D_flipflop
      port map ( clk => clock, 
                 d   => data_in(bit_index),
                 q   => data_unbuffered );
    cell_buffer : component tristate_buffer
      port map ( a  => data_unbuffered,
                 en => out_enable,
                 y  => data_out(bit_index) );
  end generate cell_array;
end architecture cell_level;

Слайд: Пример - схема (generate)

Слайд: NEW