ПЦУСБ/Лекция 5 — различия между версиями
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| − | {| cellspacing="0" cellpadding="5" border="1" | + | {| cellspacing="0" cellpadding="5" border="1" align=center |
!colspan=2| Эквивалентные описания процесса | !colspan=2| Эквивалентные описания процесса | ||
|- | |- | ||
| Строка 253: | Строка 253: | ||
* §5.2.3 Wait Statements | * §5.2.3 Wait Statements | ||
</small> | </small> | ||
| + | |||
| + | |||
| + | ==== Слайд: Оператор wait until ==== | ||
| + | |||
| + | signal clk : std_logic; | ||
| + | . . . . | ||
| + | clock_gen : process is | ||
| + | begin | ||
| + | clk <= '1' '''after''' 11 ns, '0' '''after''' 25 ns; | ||
| + | '''wait until''' clk = '0'; | ||
| + | end process clock_gen; | ||
| + | |||
| + | |||
| + | [[Файл:Wait until not clk wave.png|center]] | ||
| + | |||
| + | |||
| + | ==== Слайд: Оператор wait on ==== | ||
| + | |||
| + | {| cellspacing="0" cellpadding="5" border="1" align=center | ||
| + | |colspan=3|<pre> | ||
| + | signal clk1 : std_logic := '0'; | ||
| + | signal clk2,clk3,clk4 : std_logic; | ||
| + | .... | ||
| + | clock_gen : process is | ||
| + | begin | ||
| + | clk1 <= '1' after 11 ns, '0' after 25 ns; | ||
| + | wait until clk1 = '0'; | ||
| + | end process clock_gen; | ||
| + | </pre> | ||
| + | |- | ||
| + | |<pre> | ||
| + | pp1 : process is | ||
| + | begin | ||
| + | wait on clk1; | ||
| + | clk2 <= clk1 after 1 ns; | ||
| + | end process pp1; | ||
| + | </pre> | ||
| + | |<pre> | ||
| + | pp2 : process is | ||
| + | begin | ||
| + | clk3 <= clk1 after 1 ns; | ||
| + | wait on clk1; | ||
| + | end process pp2; | ||
| + | </pre> | ||
| + | |<pre> | ||
| + | pp3 : process (clk1) is | ||
| + | begin | ||
| + | clk4 <= clk1 after 1 ns; | ||
| + | end process pp3; | ||
| + | </pre> | ||
| + | |} | ||
| + | |||
| + | |||
| + | [[Файл:Wait on clk wave.png|center]] | ||
| + | |||
| + | |||
| + | ==== Слайд: Оператор wait for ==== | ||
| + | |||
| + | |||
| + | === Слайд: Оператор .. === | ||
Версия 17:42, 8 ноября 2013
- Заголовок
- Операторы языка VHDL
- Автор
- Авдеев Н.А.
- Нижний колонтитул
- ПЦУСБ/Лекция 5
- Дополнительный нижний колонтитул
- Авдеев Н.А., 22:33, 14 ноября 2013
Содержание |
Слайд: Последовательные операторы
- :=
- <=
- if
- case
- loop
- next
- exit
- null
- procedure call
- return
- assert
- wait
Используются в:
- process
- функциях
- подпрограммах
Слайд: Оператор присваивания: <=
conditional_waveform_assignment ::= [§ 10.5.3] target <= [ delay_mechanism ] conditional_waveforms ;
delay_mechanism ::= [§ 10.5.2.1] transport | [ reject time_expression ] inertial
Пример транспортной задержки:
transmission_line : process (line_in) is begin line_out <= transport line_in after 500 ps; end process transmission_line;
Пример инерционной задержки:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
или
y <= not a after 3 ns;
end process inv;
inv : process (a) is begin y <= reject 2 ns inertial not a after 3 ns; end process inv;
- §5.2.5 Transport and Inertial Delay Mechanisms (стр. 158)
Слайд: Оператор присваивания: <=
- EXAMPLE 5.10 An asymmetric delay element using transport delay
asym_delay : process (a) is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
begin
if a then
z <= transport a after Tpd_01;
else -- not a
z <= transport a after Tpd_10;
end if;
end process asym_delay;
Слайд: Оператор loop
- бесконечный цикл
loop_statement ⇐
[ loop_label : ] loop
{ последовательные операторы }
end loop [ loop_label ] ;
- Пример
entity counter is
port ( clk : in bit;
count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk;
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
- 3.4 Loop Statements (стр. 84 (76))
Слайд: Оператор exit
- Выход из цикла
exit_statement ::= [§ 10.2] [ label : ] exit [ loop_label ] [ when condition ] ;
- Пример
loop
if condition then
exit;
end if;
end loop;
|
loop
...
exit when ''условие'';
...
end loop;
... -- Управление перейдёт сюда
-- при выполнения условия внутри цикла loop
|
loop_name : loop ... exit loop_name; ... end loop loop_name;
Слайд: Оператор next
- Переход на следующую итерацию цикла
next_statement ::= [§ 10.11] [ label : ] next [ loop_label ] [ when condition ] ;
loop statement-1; next when condition; statement-2; end loop; |
loop
statement-1;
if not condition then
statement-2;
end if;
end loop;
|
Слайд: Оператор цикла while..loop
loop_statement ⇐
[ loop_label : ]
while condition loop
{ sequential_statement }
end loop [ loop_label ] ;
while index > 0 loop ... -- statement A: do something with index end loop; ... -- statement B
Слайд: Оператор цикла for..loop
loop_statement ⇐
[ loop_label : ]
for identifier in discrete_range loop
{ sequential_statement }
end loop [ loop_label ] ;
discrete_range ⇐ simple_expression ( to | downto ) simple_expression
for count_value in 0 to 127 loop count_out <= count_value; wait for 5 ns; end loop;
Слайд: Оператор assert (утверждение)
- проверяет условие (утверждение), в случае нарушения которого может выдаваться сообщение
concurrent_assertion_statement ⇐
[ label : ]
assert condition
[ report expression ] [ severity expression ] ;
assert initial_value <= max_value report "initial value too large";
assert current_character >= '0' and current_character <= '9' report "Input number " & input_string & " contains a non-digit";
check : assert not (s and r)
report "Incorrect use of S_R_flip_flop: " &
"s and r both '1'";
- в пакете STANDARD:
type severity_level is (note, warning, error, failure);
assert free_memory >= low_water_limit report "low on memory, about to start garbage collect" severity note;
Слайд: Оператор wait
wait_statement ⇐
[ label : ] wait [ on имя_сигнала { , ... } ]
[ until условие ]
[ for выражение_типа_time ] ;
| Эквивалентные описания процесса | |
|---|---|
half_add : process is begin sum <= a xor b after T_pd; carry <= a and b after T_pd; wait on a, b; end process half_add; |
half_add : process (a, b) is begin sum <= a xor b after T_pd; carry <= a and b after T_pd; end process half_add; |
- §5.2.3 Wait Statements
Слайд: Оператор wait until
signal clk : std_logic; . . . . clock_gen : process is begin clk <= '1' after 11 ns, '0' after 25 ns; wait until clk = '0'; end process clock_gen;
Слайд: Оператор wait on
signal clk1 : std_logic := '0';
signal clk2,clk3,clk4 : std_logic;
....
clock_gen : process is
begin
clk1 <= '1' after 11 ns, '0' after 25 ns;
wait until clk1 = '0';
end process clock_gen;
| ||
pp1 : process is
begin
wait on clk1;
clk2 <= clk1 after 1 ns;
end process pp1;
|
pp2 : process is
begin
clk3 <= clk1 after 1 ns;
wait on clk1;
end process pp2;
|
pp3 : process (clk1) is
begin
clk4 <= clk1 after 1 ns;
end process pp3;
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