Спец курс (Избранные главы VHDL)/Вспомним VHDL — различия между версиями

entity add1 is
  port (b1,b2 : in  BIT;
        c1,s1 : out BIT);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;

entity add2 is
  port (c1, a1, a2 : in  BIT;
        c2, s2     : out BIT);
end add2;
 
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and  a1 and (not a2)) or
        ( c1 and (not a1)and (not a2) ) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

entity mult_2 is
port (s1,s0,r1,r0 : in BIT;
        t3,t2,t1,t0 : out BIT);
end mult_2;
 
architecture structure of mult_2 is
component add1
port (b1,b2: in BIT;
      c1,s1: out BIT);
end component;
 
signal p1,p2,p3,p4 : BIT;
begin
t0 <= r0 and s0; -- элемент el_1
p2 <= r0 and s1; -- элемент el_3
p1 <= r1 and s0; -- элемент el_2
p4 <= r1 and s1; -- элемент el_4
circ1: add1 port map (p1, p2, p3,t1);
circ2: add1 port map (p3,p4,t3,t2);
end structure;

entity adder_2 is
port (a1, b1, a2,b2 : in BIT;
       c2,s2,s1 : out BIT);
end adder_2;
 
architecture structure of adder_2 is
component add1
 port (b1,b2: in BIT;
       c1,s1: out BIT);
end component;
 
component add2
 port(c1, a1,a2:in BIT;
      c2,s2:out BIT);
end component;
signal c1: BIT;
begin
 
circ1: add1 port map (b1,b2, c1,s1);
circ2: add2 port map (c1,a1,a2,c2,s2);
end structure;

entity vlsi_1 is
port (a2, a1, b2,b1,x:in BIT;
       d4,d3,d2,d1: out BIT);
end vlsi_1;
architecture structure of vlsi_1 is
 
component adder_2 -- декларация компонента
port (a1,b1,a2,b2: in BIT;
       c2,s2,s1: out BIT);
end component;
component mult_2 -- декларация компонента
port(s1,s0, r1,r0: in BIT;
      t3,t2,t1,t0: out BIT);
end component;
component dd -- декларация компонента
port (x1,x2,x3,x4,x5,x6 : in BIT;
      y1,y2,y3 : out BIT);
end component;
component yy -- декларация компонента
port(a2,a1,b2,b1,x : in BIT;
      f6,f5,f4,f3,f2,f1 : out bit);
end component;
signal f1,f2,f3,f4,f5,f6,t4,t3,t2,t1,c2,s2,s1: BIT;  --  декларация внутренних сигналов
 
begin
circ1: yy port map (a2,a1, b2,b1, x, f6,f5,f4,f3,f2,f1);
circ2: mult_2 port map (f2,f1, b2,b1, d4,t3,t2,t1);
circ3: adder_2 port map (f4,f3, f6,f5,c2,s2,s1);
circ4: dd port map (s1,t1,s2,t2,c2,t3, d1,d2,d3);
end structure;

entity YY is
port (a2,a1,b2,b1, x : in BIT;
        f6,f5,f4,f3,f2,f1 : out BIT);
end YY;
architecture struct_1 of YY is
begin
f1<= x and a1;
f2<= x and a2;
f3<= not x and a1;
f4 <= not x and a2;
f5 <= not x and b1;
f6 <= not x and b2;
end struct_1;

entity dd is
port (x1,x2,x3,x4,x5,x6 : in BIT;
        y1, y2, y3  : out BIT);
end dd;
architecture struct_1 of dd is
begin
y1<= x1 or x2;
y2<= x3 or x4;
y3<= x5 or x6;
end struct_1;

entity vlsi_1 is
port (a, b : in integer range 0 to 3;
      x : in BIT;
      D : out integer  range 0 to 15);
end vlsi_1;
 
architecture functional of vlsi_1 is
signal e: integer range 0 to 15;
begin
p0: process(a, b, x)
begin
if (x='0') then
e <= a + b;
elsif (x = '1') then
e <= a * b ;
end if;
end process;
D <= e;
end functional;

package multiplexer is
   procedure MX(
      signal SEL  : in  bit;
      signal x0 : in  bit;
      signal x1 : in  bit;
      signal F : out bit);
end multiplexer;
package body multiplexer is
   procedure MX(
      signal SEL  : in  bit;
      signal x0 : in  bit;
      signal x1 : in  bit;
      signal F : out bit) is
   begin
      case SEL is
         when '0'    => F <= x0;
         when others => F <= x1;
      end case;
   end MX;
end multiplexer;

entity ANDOR is
            port (x1, x2, x3 :     in bit;
                  f       :       out bit);
end ANDOR;
architecture RTL1 of ANDOR is
begin
   f <= (x1 and x2) or x3;
end RTL1;
architecture RTL2 of ANDOR is
   signal w : bit;
begin
   w <= x1 and x2;
   p1 : process (w, x3)
   begin
      f <= w or x3;
   end process p1;
end RTL2;

entity ANDOR is
            port(      x1, x2, x3 :    in bit;
                         f :   out bit);
end ANDOR;
architecture example of ANDOR is
   signal w : bit;
begin
   p0 :  w <= x1 and x2 after 10 ns;
   p1 : process (w, x3)
   begin
      f <= w or x3 after 20 ns;
   end process p1;
end example;

     entity VAR is
     end VAR;
     architecture functional of VAR is
     signal A, B, J  : bit_vector(1 downto 0);
     signal E, F, G  : bit;
     begin
     p0 : process (A, B, E, F, G, J)
     variable C, D, H, Y : bit_vector(1 downto 0);
     variable W, Q       : bit_vector(3 downto 0);
     variable Z          : bit_vector(0 to 7);
     variable X          : bit;
     variable DATA   : bit_vector(31 downto 0);
     begin
     C         := "11";
     X         := E and F;
     Y         := H nand J;
     Z(0 to 3) := C & D;            --  конкатенация
     Z(4 to 7) := (not A) & (A nor B);   -- конкатенация
     D         := ('0', '0');             --  агрегат
     W  := (2 downto 1 => G, 3 => '1', others => '0');  -- агрегат
     DATA      := (others => '1');                -- агрегат
     end process;
     end functional;

entity IFSTMT is
   port (
      RSTn, CLK, EN, PL : in  bit;
      DATA              : in  integer range 0 to 31;
      COUNT             : out integer range 0 to 31);
end IFSTMT;
architecture RTL of IFSTMT is
   signal COUNT_VALUE : integer range 0 to 31;
begin
   p0 : process (RSTn, CLK)
   begin
      if (RSTn = '0') then
         COUNT_VALUE <= 0;
      elsif (CLK'event and CLK = '1') then
         if (PL = '1') then
            COUNT_VALUE <= DATA;
         elsif (EN = '1') then
            if (COUNT_VALUE = 31) then
               COUNT_VALUE <= 0;
            else
               COUNT_VALUE <= COUNT_VALUE + 1;
            end if;
         end if;
      end if;
   end process;
   COUNT <= COUNT_VALUE;
end RTL;

entity example_condition is
   port (
      x1, x2, x3, x4 : in bit;
    condition          : in  bit_vector(1 downto 0);
      F                : out bit);
end example_condition;
 
architecture first of example_condition is
begin
   F <= x1 when condition = "00" else
        x2 when condition = "01" else
        x3 when condition = "10" else
        x4;
end first;
 
architecture second of example_condition is
begin
   process (x1, x2, x3, x4, condition )
   begin
      if (condition = "00") then
         F <= x1;
      elsif (condition = "01") then
         F <= x2;
      elsif (condition = "10") then
         F <= x3;
      else
         F <= x4;
      end if;
   end process;
end second;

entity example_selection is
   port (         x1, x2, x3, x4 : in  bit;
                       selection : in bit_vector(1 downto 0);
                               F : out bit);
end example_selection;
 
architecture first of example_selection is
begin
   with selection select
   F <= x1 when "00",
        x2 when "01",
        x3 when "10",
        x4 when others;
end first;
 
architecture second of example_selection is
begin
   process (x1, x2, x3, x4, selection)
   begin
      case selection is
         when "00"   =>   F <= x1;
         when "01"   =>   F <= x2;
         when "10"   =>   F <= x3;
         when others =>   F <= x4;
      end case;
   end process;
end second;

entity DFF is
        port (
           RSTn, CLK, D : in  bit;
           Q            : out bit);
     end DFF;
architecture RTL of DFF is
begin
        process (RSTn, CLK)
       begin
           if (RSTn = '0') then
              Q <= '0';
           elsif (CLK'event and CLK = '1') then
              Q <= D;
           end if;
        end process;
     end RTL;

    entity SHIFT is
        port (
           RSTn, CLK, SI : in  bit;
           SO            : out bit);
     end SHIFT;
     architecture RTL1 of SHIFT is
        component DFF
        port (
           RSTn, CLK, D : in  bit;
           Q            : out bit);
        end component;
        signal T : bit_vector(6 downto 0);
     begin
        bit7 : DFF
            port map (RSTn => RSTn, CLK => CLK, D => SI, Q => T(6));
        bit6 : DFF
            port map (RSTn, CLK, T(6), T(5));
        bit5 : DFF
            port map (RSTn, CLK, T(5), T(4));
        bit4 : DFF
            port map (CLK => CLK, RSTn => RSTn, D => T(4), Q => T(3));
        bit3 : DFF
            port map (RSTn, CLK, T(3), T(2));
        bit2 : DFF
           port map (RSTn, CLK, T(2), T(1));
        bit1 : DFF
           port map (RSTn, CLK, T(1), T(0));
        bit0 : DFF
           port map (RSTn, CLK, T(0), SO);
     end RTL1;

entity adder_N_comp is
port (a, b : in bit_vector (0 to 6);
        s : out bit_vector (0 to 6);
        c  : out bit);
end adder_N_comp;
architecture structural of adder_N_comp is
component add1
port (b1,b2: in BIT;
      c1,s1: out BIT);
end component;
component add2
port(c1, a1,a2:in BIT;
      c2,s2:out BIT);
end component;
signal c_in : bit_vector (0 to 5);
begin
p0: add1    port map (b1 => a(0), b2 => b(0), c1 => c_in(0), s1 => s(0));
p1: add2    port map (c1=>c_in(0), a1=>a(1), a2=>b(1), c2=>c_in(1), s2=>s(1));
p2: add2    port map (c1=>c_in(1), a1=>a(2), a2=>b(2), c2=>c_in(2), s2=>s(2));
p3: add2    port map (c1=>c_in(2), a1=>a(3), a2=>b(3), c2=>c_in(3), s2=>s(3));
p4: add2    port map (c1=>c_in(3), a1=>a(4), a2=>b(4), c2=>c_in(4), s2=>s(4));
p5: add2    port map (c1=>c_in(4), a1=>a(5), a2=>b(5), c2=>c_in(5), s2=>s(5));
p6: add2    port map (c1=>c_in(5), a1=>a(6), a2=>b(6), c2=>c, s2=>s(6));
end structural;

    entity SHIFT is
        port (
           RSTn, CLK, SI : in  bit;
           SO            : out bit);
     end SHIFT;
architecture RTL2 of SHIFT is
   component DFF
   port (
      RSTn, CLK, D : in  bit;
      Q            : out bit);
   end component;
   signal T : bit_vector(6 downto 0);
begin
   g0 : for i in 7 downto 0 generate
      g1 : if (i = 7) generate
         bit7 : DFF
       port map (RSTn => RSTn, CLK => CLK, D => SI, Q=> T(6));
      end generate;
      g2 : if (i > 0) and (i < 7) generate
         bitm : DFF
            port map (RSTn, CLK, T(i), T(i-1));
      end generate;
      g3 : if (i = 0) generate
         bit0 : DFF
            port map (RSTn, CLK, T(0), SO);
      end generate;
   end generate;
end RTL2;